The present invention pertains to processing wafers, and in particular to measuring parameters indicative of the quality of the wafer processing.
Chemical-mechanical polishing (CMP) is a well-known process in the semiconductor industry used to remove and planarize layers of material deposited on a semiconductor device to achieve a planar topography on the surface of the semiconductor device. To remove and planarize the layers of the deposited material, including dielectric and metal materials, CMP typically involves wetting a pad with a chemical slurry containing abrasive components and mechanically polishing the front surface of the semiconductor device against the wetted pad to remove the layers of deposited materials on the front surface of the semiconductor device and planarize the surface.
FIG. 1 is a schematic view of a prior art CMP apparatus 10. CMP apparatus 10 includes a wafer carrier 11 for holding a semiconductor wafer 12 having a surface 12S to be polished. Wafer carrier 11 is mounted for continuous rotation about an axis A1 in a direction indicated by arrow 13 via a drive motor 14 operatively connected to the wafer carrier. Wafer carrier 11 is adapted so that a force indicated by arrow 15 is exerted on semiconductor wafer 12.
CMP apparatus 10 also includes a polishing platen 16 mounted for continuous rotation about an axis A2 in a direction indicated by arrow 17 by a drive motor 18 operatively connected to the polishing platen. A polishing pad 19, formed of a material such as blown polyurethane, is mounted to polishing platen 16. A polishing slurry containing an abrasive fluid, such as silica or alumina abrasive particles suspended in either a basic or an acidic solution, is dispensed onto polishing pad 19 through a conduit 20 arranged adjacent the polishing pad, from temperature controlled reservoir 21.
Wafer carrier 11 rotates in a direction indicated by arrow 13 about axis A1. Polishing platen 16 rotates in a direction indicated by arrow 17 about axis A2. The polishing slurry is dispensed onto polishing pad 19 through conduit 20, from temperature controlled reservoir 21 as the wafer carrier and polishing platen rotate about their respective axes. The force between the polishing platen and the wafer carrier and their relative rotation, in combination with the mechanical abrasion and chemical effects of the slurry, serve to polish wafer surface 12S.
FIG. 2 illustrates a semiconductor device prior to CMP. As shown, substrate 12 has a source region 112 and a drain region 114, and also includes lightly doped drains 116 and 118. Source and drain regions 112 and 114 are formed according to conventional processes, after formation of a gate oxide layer 122 and gate 124. Following formation of gate 124, a first inter-level dielectric (ILD) layer 120 is deposited over gate 124. First ILD layer is 120 formed of silicon dioxide, but may be formed of other dielectric materials.
After formation of first ILD layer 120, the layer is etched to form an opening that is filled with tungsten to form a contact plug 126, which provides ohmic contact to source region 112. Although not shown in the plane of the cross-section of FIG. 2, a similar contact plug is formed for drain region 114.
Thereafter, a first metal layer 128 is deposited on first ILD layer 120. First metal layer 128 is formed of a metal, such as copper, aluminum, or tungsten. A second ILD layer 130, an etch stop layer (not shown), and a third ILD layer 134 are then consecutively formed on the first metal layer 128. Layer 130, the etch stop layer and layer 134 are formed, patterned and etched according to conventional techniques to form openings, particularly via holes 136a and trenches 138a, via holes 136a being contiguous with respective trenches 138a. That is, each via hole shares a common, upper boundary at the interface between the via hole and the trench, where the via opens into the trench. According to the structure shown, a dual-inlaid process is used to deposit a second metal layer 139 simultaneously within via holes 136a and trenches 138a to form vias 136 and interconnects 138 (i.e., lines). The third ILD layer 134 includes fine pitch dielectric portions 134a separating interconnects 138 from each other. Second metal layer 139 may be copper, aluminum or tungsten. In each case, the metal is put down in layer form on the order of 3,000 to 11,000 angstroms in thickness.
Once the basic structure of FIG. 2 is in place, CMP is carried out using CMP apparatus 10 of FIG. 1 to remove that portion of metal layer 139 above trenches 138a such that the trenches 138a form separate interconnects 138, and the exposed surface of the semiconductor device is polished and planarized for subsequent deposition steps, such as higher-level metal interconnects. With reference now to FIG. 3A, it is preferred that metal layer 139 be removed by polishing such that dielectric portions 134a separate trenches 138, with upper surface 12S being planarized.
With reference now to FIG. 3B, it often occurs that some of the metal layer 139 is not entirely removed, leaving a xe2x80x9cresiduexe2x80x9d 150 of material (here, a portion of metal layer 139). Generally, residue is any material that is supposed to have been removed from the surface of the wafer during processing. Residue generally occurs in a region that has not been polished sufficiently. Residue 150a lies over the narrow dielectric spaces of the structure, and residue 150b lies over the dielectric field.
The presence of residue 150 is problematic because it is not part of the planned semiconductor structure and thus will, in all likelihood, interfere with the performance of the resulting device. For example, in FIG. 3B, residue 150 short-circuits interconnects 138. Thus, the wafer shown in FIG. 3B would need to be re-polished, re-processed, or scrapped, unless the amount of residue was deemed minimal enough to allow the wafer to continue on to the next process.
Unfortunately, the most effective method presently available for determining if residue is present on a wafer appears to be visual inspection of the wafer surface after it has been polished. This is a time-consuming and labor-intensive process. Accordingly, it would be preferred to have an automated, time-saving way to assess the presence or absence of residue.
One approach to measuring residue is to treat the thin layer of typically metalic residue as a transparent film, and to measure its thickness as part of an homogenous film stack with an instrument like the KLA/Tencor UV1050, available from KLA/Tencor, Inc. This method is suitable for measuring residue 150b overlying a large area of field dielectric, but has a general requirement that constrains its utility. The region where the residue measurement is made must be laterally homogeneous, i.e., the stack must include only flat layers that are substantially uniform over the dimensions of the spot size of the instrument, down to the first opaque layer below the residue. This is a serious limitation since the process in question may leave residue over structures that are laterally heterogeneous over the spot size of the instrument.
For example, with reference to FIG. 4, residue 150a is in the vicinity of interconnects 138, which, in a modern integrated circuit, can have dimensions of 250 nm or less, whereas optical instruments typically have a measurement spot-size of several microns or tens of microns. Since these features are smaller than the wavelength of light, it is not possible to focus between the features, making this method unsuitable for measuring such residue.
With reference now to FIG. 5, it often occurs that some regions polish faster than others causing erosion 160 and dishing 162. In the example shown, the polish process was designed to remove metal 139 (FIG. 2), and so removes dielectric 134 more slowly. As a result, after the polishing reaches the top of dielectric 134 the metal polishes faster than the dielectric. Generally some degree of overpolish is necessary to insure that there is no residue, as discussed above. In an array area, the rapid polishing of the metal causes dishing 162 of metal lines 138 with respect to dielectric spaces 134a, and erosion 160 of dielectric lines 134a with respect to the neighboring field dielectric 134b. 
The presence of dishing and erosion are problematic for a number of reasons. The sum of dishing and erosion constitutes metal loss of lines 138. Metal loss raises the resistance of such lines, where resistance is typically critical because the lines are narrow. The higher resistance can degrade device performance. Dishing and erosion also cause an undesirable lack of planarity. Lack of planarity on the current polished surface frequently leads to lack of planarity of the next, higher polished surface, especially when the processes that deposit the overlying layers are conformal and not planarizing. Thus, locations over dished or eroded regions are lower than the surrounding areas and prone to having residue, which is a severe problem, as discussed above. Finally, lack of planarity on the overlying surfaces can degrade the results of microlithography. As device sizes shrink, the wavelength of light used in photolithography has decreased, and the numerical apertures of the lenses has increased, leading to a reduced depth of focus. This means that the distance between the lens and the substrate being exposed is a critical process parameter. If the substrate is not planar, it is impossible to have the whole surface exposed while in proper focus. Again, lack of focus during lithography can either degrade device performance, or in severe cases, result in non-functional devices. Dishing and erosion, once detected on a particular substrate, can not be repaired. Thus, the CMP process must be designed and controlled to minimize dishing and erosion.
The most effective method presently available for measuring dishing and erosion is with a stylus profiler or other scanning profiler, like an atomic force microscope (AFM). Unfortunately, these measurements have a number of disadvantages for routine use during the fabrication. They tend to be slow, and therefore delay the manufacturing process. As they employ contact or near contact, their use on product samples is generally regarded as a risk. The measurements are very sensitive to vibration, and thus not well suited for integration into a CMP cluster tool, if that is desired. Accordingly, it would be preferred to have a non-contact, fast, vibration-insensitive way to measure erosion and/or dishing.
Finarov et al. disclose in U.S. Pat. No. 6,100,985 (the ""985 patent) an optical method and apparatus suitable for measuring erosion and residue on arrays (hereinafter referred to as xe2x80x9cthe Finarov techniquexe2x80x9d). The ""985 patent is incorporated by reference herein. As illustrated in FIGS. 6a and 6b, the Finarov technique involves illuminating periodically patterned sample (array) 301 with broadband light beam 308 over a spot 310 that is larger than the pitch of the array defined by the spatial alternation of at least two zones 304 and 306. The technique detects the intensity of specularly scattered light from the array, and fits a simple model to the detected spectrum in order to measure at least one parameter (e.g., film thickness) of the array.
A suitable apparatus 320 for practicing the Finarov technique is shown in FIG. 7. Illuminator 322 emits light 324, which is deflected by beamsplitter 326 towards sample 321. Focusing element 328 focuses light 330 onto sample 321, and collimates reflected light 332, which passes back through beamsplitter 326. Turn mirror 334 deflects the collimated light 336 through second focusing element 338. Aperture stop 340 is substantially in an aperture plane for optical system 320, so that it limits light that is detected by a spectroscopic detector system 344 to only specular reflections from sample 321. Processor 346 processes the spectroscopic, specular data from detector system 344 to measure at least one parameter of sample 321.
The requirements for detecting specularly scattered light can be understood with reference to FIG. 8. Plane 348 represents an aperture plane of the optics, where distance from axis 352 represents the angle of light at sample surface 350 measured from axis 352, with positive angles corresponding to clockwise rotation about the intersection of surface 350 and axis 352. The illumination cone 351 in the aperture plane extends from point a1 identified by location 354 to point a2 identified by location 356. The reflected light is broken into diffraction orders by periodic array 350. The specular or zeroth order reflected cone overlaps incident cone 351, with the illumination ray eminating from a1 giving rise to a reflected ray reaching the aperture plane at a2, and vice versa, for the illustrated situation of quasi-normal illumination, i.e., where the axis of the illumination cone lies substantitally along axis 352. xe2x80x98Specularxe2x80x99 means xe2x80x9cas from a mirrorxe2x80x9d. This is the only component of light that would be reflected from a mirror. Non-specular reflected cone 363 represents first-order diffracted rays which exend on the aperture plane from point b1 identified by location 364 to point b2 identified by location 366. The Finarov method is particularly directed towards periodic samples. For such samples, non-specular light is reflected as discrete orders, as is well known in the art. The distance of a point on aperture plane 348 from axis 352 is proportional to the sine of the angle of a ray that passes through that point. For simplicity of notation, the constant of proportionality is taken as unity without loss of generality. It would have some other value in a practical situation. The sine of a diffracted ray of order n due to an incident ray of sine a is given as
b=a+ndxe2x80x83xe2x80x83Eq. 1 
where d=w/p is the ratio of wavelength w and period p of array 350. Thus, the illumination ray emanating from location 354 gives rise to the scattered first-order (n=1) ray reaching aperture plane 348 at location 364, and the illuminating ray from 356 gives rise to the scattered ray at 366.
The Finarov technique places stop 340 in the detection optics so that only rays that reach aperture plane 348 between points c1 identified by location 360 and c2 indentified by location 362 reach detector 344. The necessary constraint for the placement of c2 so that only specular rays are detecteded applies for the shortest wavelength w1 and first-order ray at b1 364 which is closest to axis 352:
c2 less than b1xe2x80x83xe2x80x83Eq. 2 
In order to generalize this constraint, it is convenient to define the numerical apertures a0 of the illumination optics and c0 of the detection optics so that a1=xe2x88x92a0, a2=a0, c1=xe2x88x92c0, and c2=c0. Then, the general constraint to insure substanitally specular detection of light reflectected by sample 301 is:
a0+c0 less than w/pxe2x80x83xe2x80x83Eq. 3 
The constraint in Equation 3 has several disadvantages. First, the method requires that the sample have a periodic structure. It does not apply to aperiodic sample structures where diffraction orders are not well defined. Also, it requires a priori knowledge of the sample pitch p. It also requires an adjustable stop, with the associated additional complexity of hardware, electronics and software to control the stop. Finally, the constraint reduces the amount of light that reaches the detector and contributes to the measurement. In other words, it reduces the signal-to-noise ratio of the system, all else being equal. Collecting light at the detector for a longer time can improve the signal-to-noise ratio, but would reduce the throughput of the system, which is undesirable in a manufacturing environment.
The present invention pertains to processing wafers, and in particular to measuring parameters indicative of the quality of the wafer processing.
An object of the present invention is provide the optical method and aparatus to measure at least one parameter of a structure which is heterogeneous over the spot size of the optical system with as few limitations on applicability and design of the optical system as possible, and requires as little a priori information about the sample as possible.
It is another object of the present invention to provide a fast and robust means for characterizing dishing, erosion and residue of structures employed in microelectronic devices, e.g., integrated circuits. Depending on the situation in the factory, the hardware to make such measurements could be integrated into a process tool, such as a tool for chemical mechanical polishing (CMP), or on its own platform as a stand-alone tool.
It is another object of the present invention to provide a way to control the fabrication of microelectronic devices to minimize the occurance of dishing and erosion, on the one hand, and residue, on the other. Control of the process involves measuring the results of a process step and either feeding those results back to adjust the process for subsequent samples, or feeding the information forward to adjust subsequent processing steps.
Accordingly, a first aspect of the present invention is a method of measuring at least one parameter associated with a portion of a sample having formed thereon one or more structures with at least two zones each having an associated zone reflectance property. The method includes the steps of illuminating the zones with broadband light, and measuring at least one reflectance property of light reflected from the at least two zones. This reflectance property may be, for example, intensity. The measurement includes a substantial portion of non-specularly scattered light, thereby increasing the quality of the measurement. The method further includes the step of fitting a parameterized model to the measured reflectance property. The parameterized model mixes the zone reflectance properties of the zones to account for partially coherent light interactions between the two zones.
A second aspect of the invention is a method of measuring at least one final measured parameter associated with a portion of a sample having formed thereon having one or more structures. The method includes the steps of illuminating the sample at a first location with broadband light, and measuring at least one reflectance property of light reflected from the first location. The method further includes the steps of illuminating the sample at a second location having at least two zones, with broadband light and measuring at least one reflectance property of light reflected from the at least two zones. The next steps include fitting a first parameterized model to the first reflectance property to obtain an intermediate measured parameter, and fitting a second parameterized model to the second measured reflectance property based upon the first measured parameter. The second reflectance model accounts for light interactions the at least two zones to obtain a value for the at least one final parameter.